1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly to the detection of a lack of adhesion (i.e., delamination) at interfaces within a processed semiconductor wafer.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements, often called interconnect lines (i.e., interconnects). Interconnects are patterned from conductive layers formed on or above the surface of a silicon substrate. One or more conductive layers may be patterned to form one or more levels of interconnects vertically spaced from each other by one or more interlevel dielectric layers. Common materials for interlevel dielectric layers include silicon dioxide (i.e., oxide), silicon nitride, and polyimide. Dielectric-spaced interconnect levels allow formations of densely patterned devices on relatively small surface areas. Interconnects on different levels are commonly coupled electrically using contact structures formed in vias (i.e., holes etched through the interlevel dielectric layers separating the interconnects).
The operating speed of an integrated circuit is limited by transistor switching times and signal propagation delays associated with signal lines along one or more critical signal paths through the circuit. A signal line formed between input/output terminals of an integrated circuit comprises interconnects arranged on one or more levels, connected by contact structures (i.e., contacts) disposed between the interconnect levels. The resistance of each signal line is equal to the sum of the resistance values of the interconnect lines and the contacts making up the signal line.
As feature sizes shrink, transistor switching times typically decrease while signal propagation delays of signal lines typically increase. In fact, the maximum operating speeds of integrated circuits with submicron feature sizes are typically limited by signal propagation delays associated with signal lines. Thus if the maximum operating speeds of integrated circuits are to increase as device dimensions shrink, the resistance values associated with interconnect lines and contacts must also be reduced to achieve a desired increase in operating speed.
Interconnect lines may be formed by stacking layers of various electrically conductive materials (e.g., metals) on top of one another. Currently, such metal stacks commonly include titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), and alloys of these metals. One important characteristic of an interconnect line is that it must adhere to underlying structures (e.g., an interlevel dielectric layer, single and polycrystalline silicon, metallic silicides, etc.). Multiple interfaces are created within interconnect lines formed by such vertical stacking of layers of conductive materials. Stresses develop across each interface to accommodate the differences in microstructures and other properties including thermal expansion coefficients. These stresses can lead to a loss of adhesion at one or more of the interfaces (i.e., delaminations at one or more of the interfaces). In addition, contamination of an interface during manufacture may also lead to subsequent delamination at the interface.
Delamination at any such interface may deleteriously affect the operation and reliability of a device including the interconnect line. Currently, the only methods for determining whether delamination has occurred include optical and electron microscopy. Both techniques are slow and time consuming, allowing only a limited portion of an integrated circuit to be examined in a reasonable amount of time. Thus current techniques for determining whether delamination has occurred cannot be used efficiently in a manufacturing environment subject to volume production.
It would be beneficial to have a test structure and associated method which allow a quick and easy determination of whether delamination has occurred within an interconnect line formed by stacking layers of various conductive materials. Such a test structure and method would be useful in manufacturing environments where integrated circuits are produced in volume.